In many of today's micro-electronics, smaller more compact sizing yields greater speed and processing power. Improved materials and precision in manufacturing permit greater resolution in semiconductor manufacturing.
Today's computer systems employ a variety of different types of semiconductors, such as processors and memory. Increased speed and sophistication of these systems is due in large part to reductions in the size of the semiconductor components. For example, whereas 32 megabytes of memory was once considered large, contemporary computer systems may provide several gigabytes in substantially the same physical space.
With respect to semiconductor memory structures, and specifically magnetic tunnel junction structures such as MRAM, the principle underlying the storage of data in a magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit (i.e., the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher its coercivity.
A prior art magnetic memory cell may be a tunneling magnetoresistance memory cell (TMR), a giant magnetoresistance memory cell (GMR), or a colossal magnetoresistance memory cell (CMR), each of which generally include a data layer (also called a storage layer or bit layer), a reference layer, and an intermediate layer between the data layer and the reference layer. The data layer, the reference layer and the intermediate layer can be made from one or more layers of material.
The data layer is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization of the data layer representing the logic state can be rotated (switched) from a first orientation, representing a logic state of “0”, to a second orientation, representing a logic state of “1”, and/or vice versa.
The reference layer is usually a layer of magnetic material in which an orientation of magnetization is “pinned”, as in fixed, in a predetermined direction. Often several layers of magnetic material are required, and function as one to effectuate a stable, pinned reference layer. The predetermined direction is determined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, when an electrical potential bias is applied across the data layer and the reference layer in a MTJ cell (also known as a tunnel junction memory cell), electrons migrate between the data layer and the reference layer through the intermediate layer. The intermediate layer is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling.
The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data storage layer is parallel to the pinned orientation of magnetization in the reference layer, the magnetic memory cell will be in a state of low resistance. If the overall orientation of the magnetization in the data storage layer is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer, the magnetic memory cell will be in a state of high resistance.
Main memory devices such as MRAM often employ tunnel junction magnetic memory cells positioned at the transverse intersections of electrically conductive rows and columns. Such an arrangement is known as a cross-point memory array.
In a typical cross-point memory array, while any given row (row A, B, C . . . ) may cross every column (column 1, 2, 3 . . . ), and visa-versa, the traditional principles of column and row arrays dictate that any given row will only cross any given column once. Therefore, by accessing a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B,3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities.
The data layer and reference layer may be thought of as stacked bar magnets, each long on the X axis and short on the Y axis. The magnetization of each layer has a strong preference to align along the easy axis, generally the long X axis. As with traditional bar magnets, the data layer and reference layer each have magnetic poles, one at either end of the easy axis. The lines of magnetic force that surround the data and reference layers are three-dimensional and flow from the North to the South pole.
The influence of the magnetic force surrounding a bar magnet can be widespread. A significant amount of space in an MRAM structure may be devoted to buffering space between MTJ cells so that the field of one MTJ does not inadvertently affect the field of a neighboring MTJ cell.
Ring magnets, otherwise known as toroidal or annular magnets, provide a substantially closed field. As the magnetic flux goes around the ring and closes upon itself, the amount of fringe field emanating from the lateral ends or from the top and bottom is minimized. Because of this, annular magnets generally can be placed side by side in close proximity. An important aspect of the annular magnet is its central hole, as the size and location of the hole directly affects the magnitude and profile of the magnetic field inside the magnet ring.
Generally speaking, semiconductors are manufactured through a layering process that provides two or more patterned conductive layers separated by intervening insulation layers. Considering the layers to be horizontally stacked, vertical points of contact between two or more conductive layers through the insulation layers are known as via structures, or more generally, via contacts. It is these via contacts that provide the wiring pattern for the semiconductor integrated circuit.
Throughout the history of manufacturing components, in almost all cases, the quality of production may be increased while costs are decreased when methods are found to simplify the processes. With respect to semiconductors and nano-scaled components, the use of photolithography is well known. Generally speaking, a layer of material is set down on a substrate. A photo-resist layer, also commonly know simply as a photoresist, or even resist, is then applied typically with a spin coating machine. A mask is then placed over the photoresist and light, typically ultra-violet (UV) light, is applied.
During the process of exposure, the photoresist undergoes a chemical reaction. Generally the photoresist will react in one of two ways. With a positive photoresist UV light changes the chemical structure of the photoresist so that it is soluble in a developer. What “shows” therefore goes, and the mask provides an exact copy of the pattern which is to remain. A negative photoresist behaves in the opposite manner—UV exposure causes it to polymerize and therefore resists dissolving by the developer. As such, the mask is a photographic negative of the pattern to be left. Following the developing process, “blocks” of photoresist remain. These blocks may be used for a variety of purposes, such as to protect portions of the initial layer during further processing or to serve as isolators or other components.
In many cases, the defined structures achieved by the masked and developed photoresist are repeated many times across a given layer. The masking process and the developing process do have inherent error margins. Further, as the creation of a mask is typically complex and cost intensive, use of a single large mask to mask an entire substrate all at once may not be desired. As a result, a smaller mask may be used repeatedly to achieve the affect of a single large mask; however, misalignment of the repeated maskings may waste material and/or result in an unusable wafer. In addition, the steps of masking and developing are distinct and each may require separate devices and setup times.
As noted above, vertical interconnections between layers are important aspects in semiconductor fabrication. For the application of an annular magnetic layer, a vertical interconnection will define the central hole and therefore affect the quality of the magnetic field. Prior art methods to accomplish conductive vertical interconnections between layers of materials have generally followed one of two paths. In one, a physical hole is etched, as in drilled, through a non-conductive layer and subsequently filled with a conductive material.
Such etching or drilling requires fine precision and control, for too much etching or drilling may damage, deplete or entirely remove the underlying layer to which the via contact is intended to contact. Akin to engraving a fine crystal bowl, the etching step occurs after the layer structures have been established. In other words, there is a substantial risk placed upon a step nearer the end of fabrication.
An alternative and potentially less risky method involves complex multi-step photolithography to define and undercut masking structures, which upon removal may provide a via contact. Whether dependent upon multiple masking, the use of resists of different developing speeds, or combinations of both, the process of providing via contacts is time consuming and difficult. Many factors can inadvertently affect the resulting size of a via contact, a factor that will directly affect the performance and ability of the semiconductor structure.
Photolithographic methods are also somewhat limited in how small a feature may be. This is in part due to each photolithographic step having inherent margins of error, which are compounded by each additional photolithographic step. Generally speaking, by making memory cells smaller, at least two important benefits result—more cells may be placed in the same physical space and the memory is likely to be faster. Presently, it has not been possible to render toroidal magnetic memory cells of a size in the 50 nm ˜150 nm range.
Hence, there is a need for a method of providing MTJ cells which overcome one or more the drawbacks identified above. The present invention accomplishes this objective.